There are known technologies for stacking semiconductor elements by solder bonding on circuit substrates and technologies for stacking plural semiconductor elements in which through silicon vias (TSV) are formed by solder bonding. The solder bonding is executed, for example, by heating to melt solders used for terminals of semiconductor elements.
Japanese Laid-open Patent Publication No. 2013-168503 and Japanese Laid-open Patent Publication No. 2013-187423 are examples of the related art.